In the circuit design of many integrated circuits, and particularly application specific integrated circuits (ASICs), significant efforts are made to design the circuit to facilitate operational testing. Operational testing refers to the testing of the circuit to determine if it performs the electrical functions it was designed to perform. In its simplest form, operational testing is performed by placing predetermined signals at the inputs of the circuit and reading the outputs to determine if they are the expected response to the selected input signals. However, rather than designing a circuit giving consideration only to the function to be performed, circuitry may be added to the design, including additional input and output pins, which will facilitate the testing of the chip.
In order to test an integrated circuit for every possible fault, one would need to input to the integrated circuit every possible combination of input states (i.e., test patterns), including every possible preceding state for circuits which include latches or other types of components with outputs that depend on a previous state, and read the outputs in response thereto. In LSI (large scale integrated) and VLSI (very large scale integrated) circuits, such exhaustive testing, particularly without modification for facilitating testability, is not feasible since the time required to perform such tests is excessive.
Typically, fault models are employed in determining and selecting the most useful test patterns for testing circuits. Using one of these fault models, a set of test patterns is generated which will test the circuitry with respect to a large proportion of possible operational faults, preferably using as few test patterns as possible. Methods exist for generating sets of test patterns. Dependent upon the circuit and the fault model used, the CPU time necessary to generate the appropriate set of test patterns can be significant. Each test pattern is placed at the inputs of a chip and the outputs in response thereto are observed. If one or more of the outputs do not match the expected results, then an operational fault is indicated.
A fault model that is used throughout the industry which covers a large majority of possible faults is known as the "Single Stuck-At" model. This model assumes that errors in the operation of an integrated circuit are the result of a single logic gate input or output being fixed to, or stuck at, either a logic 0 or a logic 1 level. A Stuck-At fault, for instance, exists where an input to a logic gate is perceived by that logic gate as a logic 1 regardless of the actual input voltage level. In the Single Stuck-At model, it is assumed that the circuit will contain one and only one stuck-at fault. Therefore, when using the single Stuck-At model, it is possible that circuits with multiple stuck-at faults will go undetected. In determining and selecting the set of test patterns to run through a given integrated circuit, it is typically desirable to test for approximately 95 to 100% of all possible single Stuck-At faults using as few test patterns as possible.
Typically, the more logic gates there are between the inputs to which the test patterns are applied (i.e., the inputs which are accessible to the tester) and the outputs from which the results are read (i.e., the outputs which are accessible), the more complicated and time-consuming are the generation of sets of test patterns as well as the actual testing.
One widely accepted method of decreasing the number of logic gates between the accessible inputs and outputs is called partitioning. The basic concept of partitioning involves isolating individual groups of logic gates from events occuring in the remainder of the integrated circuit and providing some means for a tester to be able to place signals directly at the inputs of the partitioned circuitry and to directly read the outputs of the partitioned circuitry. In this manner, the "partitioned" portions of the circuitry can be tested individually, thus reducing the overall number of test patterns necessary to adequately test the circuit. Test methods are available wherein the integrated circuit can be essentially partitioned such that individual groups of logic gates can be tested independently of the rest of the circuit. However, the added circuitry for providing the ability to partition and to directly access the partitioned circuitry, such as multiplexers for isolating individual groups of logic gates from the system clocks (partitioning) and shift registers for inputting test patterns as well as the extra pins for inputting the test patterns and reading the outputs, can greatly increase the necessary hardware. The testing overhead (the percentage of the chip circuitry which is provided for the purpose of testing) is commonly on the order of the 10-20% of the chip area.
There are two basic objectives in designing a chip for testability. The first objective is to design circuitry into the chip which increases its testability with a minimum amount of additional circuitry (hereinafter referred to as testing overhead or simply overhead). The second objective is to determine the set of test patterns to be used to test the chip which covers as many possible faults with as few test patterns as possible.
A description of many of the known testing methodologies for integrated circuits is found in Williams, T.W., & Parker K.P., DESIGN FOR TESTABILITY--A SURVEY, Proceedings of the IEEE, Vol. 71, No. 1, January 1983, pp 98-112.
One known methodology for implementing testability of an integrated circuit is the full scan method. The full scan methodology is described in detail in U.S. Pat. No. 3,784,907 issued Jan. 8, 1987, U.S. Pat. No. 3,783,254 issued Jan. 1, 1974 and U.S. Pat. No. 3,761,695 issued Sep. 25, 1973 all to Eichelberger. In the full scan methodology disclosed in these patents, every storage element is made scannable. By making every storage element directly accessible as a psuedo-primary input and output, the design is made essentially combinational. Several automatic test pattern generation algorithms exist for combinational designs.
It is relatively simple to design a circuit to implement the full scan methodology since there is no need to make decisions as to which storage elements to make scannable and which not to make scannable. Although simple to design, integrated circuits which are designed by the full scan method have a significant amount of testing circuitry overhead since every storage element is scannable.
Therefore, it is an object of the present invention to provide an improved method and apparatus for designing testability into integrated circuits.
It is another object of the present invention to provide a method of designing testability hardware into an integrated circuit design which can be implemented automatically by software.
It is one other object of the present invention to provide a methodology for testing integrated circuits and the like which requires greatly reduce circuit overhead.
It is yet a further object of the present invention to provide a method and apparatus for designing testability into an integrated circuit during the designing of the functional circuit.